Low-Power and Area Optimized AES-CMAC Architecture with LP-LFSR for Secure Data Authentication

Abstract

Secure communication systems use cipher-based Message Authentication Codes like Advanced Encryption 
Standard AES-CMAC to protect data, communications, and user authentication. Due to frequent toggling during key 
generation and simultaneous processing, classic AES-CMAC systems consume a lot of power and hardware. This 
research presents a power- and area-efficient AES-CMAC design to address these concerns. This design uses an 
optimized LP-LFSR for pseudo-random key generation. The design's capacity to process four 128-bit blocks in 
parallel makes 512-bit data stream encryption and authentication efficient. The LP-LFSR refreshes the key register 
at predefined clock intervals to reduce dynamic power consumption and switching activity while retaining 
functionality. The FPGA-based Verilog implementation combines AES encryption, CMAC authentication, decryption, 
and verification. While retaining frequency and low latency, experimental results show 5.64% and 10.75% lower 
power consumption and LUT utilization than traditional systems. Due to its balanced security, space, performance, 
and power efficiency, the suggested architecture is appropriate for low-power VLSI applications, embedded systems, 
and the IoT.