Area Optimization of Arithmetic Logic Units Using Majority Logic Gates

Abstract

Arithmetic Logic Units (ALUs) are critical to digital systems' performance, power efficiency, and space 
utilisation. In recent years, alternative logic design strategies such as reversible logic and majority logic have gained 
popularity for low-power VLSI applications. This paper compares an ALU developed using reversible logic gates to 
an ALU implemented with majority gates. The reversible-gate-based ALU uses Peres, Fredkin, and CNOT gates to 
perform arithmetic and logical operations while mini missing information loss. However, the actual implementation 
includes extra trash outputs and intricate linkages, which increases space and power consumption. In contrast, the 
majority-gate-based ALU employs compact majority logic structures to efficiently perform arithmetic and logic 
operations while reducing hardware complexity. Both designs are built and synthesised on an FPGA platform, and 
their performance is assessed using area and power metrics. The findings show that the majority-gate-based ALU 
has a much lower logic utilisation and power consumption than the reversible-gate-based ALU. As a result, the 
current majority-gate ALU is more suited to low-power, area-efficient VLSI applications