DESIGN OF FIXED-WIDTH BOOTH MULTIPLIER USING DATA SCALING METHOD FOR DSP COMPUTATIONS

Abstract

Truncation errors lead to the adverse effects in obtaining the high-speed
performance with in the DSP. Computation circuits to overcome these issues Data Scaling
Technology (DST) is used. The difference between a truncated value and the actual value is
known as Truncation error. This truncation error can be reduced by doing repeated iteration
using iterative methods.
Data Scaling Technology (DST) is used in a low error Fixed –Width Booth
Multipler (FWBM) to reduce truncation in DSP circuits. The proposed DST architecture uses
the redundant bits of the multiplicand to more efficiently obtain bits for low FWBMs. More
specifically, a Data Scaling Technology (DST) for use in a low-error Fixed-Width Booth
Multiplier (FWBM) to reduce truncation errors. The proposed DST uses the redundant bits of
the multiplicand to more efficiently obtain bits low-error FWBMs. To reduce the truncated
partial products, which are used to estimate the compensation bias. At the cost of increased
computations in the FWBM. The accuracy of the FWBM can be improved by adding the
proposed DST circuit with in the architecture by reduced area overhead and enhanced
accuracy.
Expected results indicate that the use of the proposed DST increases the accuracy of
low error FWBMs with a small area overhead by estimating delay and speed. The
effectiveness of the proposed method is designed using Verilog HDL program in Xilinx 14.7
environment.