Design And FPGA Simulation Of 4-Term Floating Point Adder With Single Normalization

Abstract

Floating-point addition is a fundamental operation in digital signal processing, scientific computing, artificial 
intelligence, and FPGA-based computing systems. Conventional IEEE 754 floating-point adders provide high 
numerical accuracy but suffer from increased latency and hardware complexity due to exponent alignment, carry 
propagation, normalization, and rounding operations. This work presents the design and FPGA implementation 
of a hardware-efficient 4-term floating-point adder with single normalization and pipelined parallel 
accumulation. The proposed architecture employs a carry-preserving parallel adder tree to perform simultaneous 
accumulation of four aligned mantissas, reducing arithmetic delay and improving throughput. A lightweight 
single-stage normalization technique minimizes hardware overhead while preserving near-monotonic arithmetic 
behavior. Pipeline registers further enhance performance by reducing the critical path. The architecture is 
implemented in Verilog HDL, verified using ModelSim, and synthesized on an Intel Cyclone V FPGA using 
Quartus Prime. Synthesis results show that the design utilizes only 334 Adaptive Logic Modules (ALMs) and 25 
registers, occupying less than 1% of the available FPGA resources. The proposed architecture achieves an 
effective balance between hardware efficiency, computational speed, and numerical accuracy, making it suitable 
for FPGA-based arithmetic accelerators and high-performance embedded computing applications.