An Analytical Study Of High-Speed Low-Power Decoder Circuits Employing Mixed Logic

Abstract

This research introduces an innovative design methodology for line decoders based on a hybrid logic framework. 
The proposed approach strategically integrates transmission gate logic, dual-value pass transistor logic, and 
conventional static CMOS logic to achieve an optimal balance between performance, power efficiency, and area 
utilization. For the 2-to-4 decoder, two distinct configurations have been developed: A 14-transistor design 
optimized for minimal transistor count and reduced power consumption. A 15-transistor design focused on superior 
power-delay product performance. 
Each of these configurations supports both fixed-function and adaptive operating modes, resulting in four unique 
decoder variants. Furthermore, four new 4-to-16 decoder architectures have been realized by combining the 
proposed 2-to-4 pre-decoder stages with traditional CMOS-based post-decoder logic. Compared to conventional 
CMOS implementations, the suggested decoders demonstrate notable advantages, including higher output voltage 
swing and a reduced overall transistor count. Comprehensive simulations performed using a 32 nm technology node 
confirm significant improvements in both power consumption and propagation delay characteristics. The hybrid 
logic strategy presented in this work offers a promising direction for designing high-performance, energy-efficient 
decoders suitable for modern VLSI applications where speed, power, and reliability are critical design constraints.