Performance Evaluation Of Proposed Compressor Architectures In Multiplier Designs
Keywords:
VLSI design, higher-order compressors, 8–4 compressor, 9–4 compressor, high-speed multiplier, energy-delay product (EDP), area optimization, low-power design, digital signal processing (DSP), arithmetic circuits.Abstract
This research introduces advanced higher-order compressor architectures specifically optimized for high-speed
and energy-efficient multiplication operations in VLSI systems. The proposed designs deliver two primary
advantages: significantly reduced computational latency and improved spatial (area) efficiency within the
multiplier structure. While lower-order compressors generally achieve a marginally better Energy-Delay
Product (EDP), their inherent limitations in delay and area make them less suitable for high-performance
applications. The trade-offs between EDP, speed, and silicon area must therefore be carefully evaluated based
on the specific requirements of the target application. To thoroughly assess the effectiveness of the proposed 8-4
and 9-4 compressors, the study implemented and analyzed multipliers of varying sizes: 8×8, 16×16, and 24×24.
These were systematically compared against conventional multiplier architectures that rely on traditional
lower-order compressor structures. Simulation results clearly demonstrate that the newly developed
compressors deliver superior performance in scenarios demanding fast multiplication. They achieve noticeable
improvements in overall speed and area utilization, making them highly effective for modern high-performance
digital systems. The proposed higher-order compressor designs successfully address many of the shortcomings
associated with conventional approaches. By offering a better balance between speed, area, and power
efficiency, they represent a meaningful advancement in multiplier optimization. These architectures are
particularly well-suited for integration into high-speed processors, digital signal processors (DSPs), and other
performance-critical VLSI applications where both latency and area constraints are paramount. The findings
from this research contribute valuable insights for future development of low-power, high-speed arithmetic
circuits and reinforce the importance of innovative compressor designs in advancing VLSI technology
