RISC V Processor Using Verilog

Abstract

The RISC-V Processor using Verilog HDL project focuses on the design and implementation of a simplified 
processor based on the open-standard RISC-V Instruction Set Architecture (ISA). The primary objective of this 
work is to understand the internal organization and functionality of a processor by developing a modular 
hardware design using Verilog Hardware Description Language (HDL). The proposed processor demonstrates 
the fundamental concepts of instruction execution, data processing, and hardware control while providing 
practical knowledge of digital system design and processor architecture. The processor is developed using a 
modular design approach, where each functional unit is implemented independently and then integrated to form 
the complete processor. The architecture consists of essential components including the Program Counter (PC), 
Instruction Memory, Control Unit, Register File, Arithmetic Logic Unit (ALU), Data Memory, and multiplexers 
required for data routing. The processor follows the standard instruction execution cycle comprising instruction 
fetch, instruction decode, execution, memory access, and write-back stages, ensuring systematic processing of 
each instruction. 
The implemented processor supports a basic set of RISC-V arithmetic and logical instructions, including addition, 
subtraction, AND, OR, and XOR operations. Functional verification is carried out through simulation using 
Verilog HDL simulation tools, where waveform analysis is used to validate the correctness of instruction 
execution, control signal generation, ALU functionality, register operations, and overall data flow. The simulation 
results confirm that the processor executes the supported instructions accurately and produces the expected 
outputs.To simplify the hardware implementation and emphasize the fundamental concepts of processor design, 
an 8-bit architecture is adopted in this project. Although advanced processor features such as pipelining, cache 
memory, hazard handling, and branch prediction are not incorporated, the developed processor successfully 
demonstrates the core principles of the RISC-V architecture. The project provides a solid foundation for learning 
processor design, computer architecture, and hardware implementation using Verilog HDL, while offering 
opportunities for future enhancement through the integration of advanced architectural features and performance 
optimization.