FPGA IMPLEMENTATION OF AN IMPROVED WATCHDOG TIMER FOR SAFETY

Abstract

When it comes to embedded systems that are used in mission-critical applications, extreme dependability
is absolutely necessary. By using external watchdog clocks, these kinds of systems are able to automatically manage
and recover from issues that are associated with operational time. In terms of functionality, the majority of the external
watchdog clocks that are now available on the market depend on additional circuitry to adjust the lengths of their
timeouts. Detailed information on an improved customisable watchdog timer that is suited for use in applications that
are mission-critical is provided in this research. The fact that the watchdog integrates a large number of fault detection
algorithms contributes to the increased dependability of the watchdog. Due to the fact that its capabilities and
operations are very extensive, it may be used to monitor the actions of any processor-based real- time system. Another
topic that is discussed in this article is a Field Programmable Gate Array (FPGA) in the construction of the
recommended watchdog timer. Because of this, the overall cost of the system is decreased, and the design is made
more easily adaptable to a variety of applications. The first step in determining how effective the recommended
watchdog timer is in detecting and responding to problems is performed by conducting an analysis of the outcomes
of the simulation. There is the possibility of doing real-time hardware validation of the design by injecting faults into
the code while the processor is running.