Efficient FIR Filter Design Employing Vedic Multiplier and Carry Lookahead Adder for DSP Applications
Keywords:
Weinberger Multiplier, Weinberger Adder,Vedic algorithm , carry look ahead adder, FIR Filter VLSI architecture and Verilog HDL.Abstract
The rising requirement for high-performance, low-power digital signal processing (DSP) systems requires efficient
arithmetic solutions, notably in Finite Impulse Response (FIR) filters, where multipliers and adders account for most
hardware expenses. To boost speed, the current FIR design makes use of Weinberger adders, composite adders, and
Weinberger-based multipliers; nonetheless, the intricate carry-generation structure and multi-stage adder trees result
in higher LUT utilization and increased dynamic power. This paper suggests an optimized FIR design that combines
a high-speed Carry Lookahead Adder (CLA) with a Vedic (Urdhva–Tiryagbhyam) 8×8 multiplier to get around these
restrictions. While the CLA greatly reduces carry propagation latency, the Vedic multiplier offers quick parallel
partial-product creation with less logic depth. In comparison to the current Weinberger-based structure, the suggested
architecture delivers lower dynamic power, fewer LUTs, and less switching activity. The suggested design improves
speed, reduces power consumption, and provides an area-efficient solution appropriate for contemporary low-power
DSP applications, according to simulation and synthesis findings in Vivado.
