Power Efficient VLSI Architecture of Fault Tolerant BIST using LCG

Abstract

The detection of faults in electronic systems is critical for ensuring reliability and optimal performance, especially
in safety-critical applications. One innovative technique for fault detection is the use of Built-In Self-Test (BIST)
technology, which integrates self-diagnostic capabilities directly into the system's architecture. This paper
explores the concept of "Stuck-at Fault" detection using BIST technology, focusing on identifying and isolating
faults where a signal is stuck at a constant logic level, either '0' or '1'. The study reviews the methodologies
employed in designing BIST systems tailored for stuck-at faults, including fault models, test pattern generation,
and fault coverage analysis. A key aspect of this research involves evaluating the effectiveness of various BIST
approaches in detecting and diagnosing stuck-at faults in combinational and sequential circuits. Through
simulations and case studies, the paper demonstrates the potential of BIST to improve fault detection accuracy,
reduce testing time, and minimize hardware overhead. The results show that BIST technology offers a costeffective,
efficient solution for enhancing fault detection capabilities in modern integrated circuits and systems